Junior VLSI Design Engineer 1204 (Tel-Aviv)
VLSI design engineer that will join Ceragon Design group.
Taking part in micro-architecture, design, IP integration and other tasks as part of the chip development processes.
- BSc in Electrical engineering from known University – Must.
- Learned VLSI in the university with a minimum rank of 85.
- Excellent communication skills in English (written and verbal) – Must.
- Script knowledge (TCL, Perl, etc.) – Advantage.
- Strong execution orientation.
- Thorough and accurate.
- Fast learning skills.
- Open minded.